RL agent learns to fix chip layouts instead of creating them from scratch
This paper proposes using Reinforcement Learning as a macro regulator instead of a macro placer to improve chip placement quality and manufacturability.
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https://arxiv.org/abs/2412.07167v1
🎯 Original Problem:
Current RL-based chip placement methods suffer from long training times, poor generalization, and unreliable PPA (Power, Performance, Area) metrics. They try to place macros from scratch, leading to limited state information and inaccurate rewards.
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🔧 Solution in this Paper:
→ MaskRegulate shifts focus from initial placement to refining existing layouts, acting as a regulator rather than a placer
→ The approach integrates regularity metrics into the RL framework, which was previously overlooked despite being crucial for manufacturability
→ It uses comprehensive state information and dense rewards by operating on pre-existing placements
→ The system combines visual information with regularity metrics to make placement decisions
→ A trade-off coefficient α balances wirelength optimization versus regularity goals
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💡 Key Insights:
→ Operating on existing placements provides better state information than placing from scratch
→ Incorporating regularity metrics significantly improves manufacturability
→ Dense rewards lead to more efficient learning and better final placement quality
→ The approach can fine-tune placements from any initial method
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📊 Results:
→ 17.08% improvement in routing wirelength
→ 73.08% and 38.81% improvement in horizontal and vertical congestion overflow
→ 18.35% improvement in worst negative slack
→ 37.89% improvement in total negative slack
→ 46.17% reduction in violation points
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